MCF5272UM/D 3/2002 REV 2
MCF5272 ColdFire(R) Integrated Microprocessor User's Manual
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors DOCUMENT COMMENTS: FAX (512) 933-2625, Attn: TECD Applications Engineering
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Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module Pulse-Width Modulation (PWM) Module Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Appendix B: Buffering and Impedence Matching Index
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Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module Pulse-Width Modulation (PWM) Module Signal Descriptions Bus Operation IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Appendix B: Buffering and Impedence Matching Index
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CONTENTS
Paragraph Number Title Page Number
Chapter 1 Overview
1.1 1.2 1.2.1 1.2.2 1.2.2.1 1.2.2.2 1.2.2.3 1.2.2.4 1.2.2.5 1.2.2.6 1.2.3 1.2.4 1.2.5 1.3 1.3.1 1.4 1.4.1 1.4.2 1.4.3 1.4.4 MCF5272 Key Features...................................................................................... MCF5272 Architecture ....................................................................................... Version 2 ColdFire Core................................................................................. System Integration Module (SIM).................................................................. External Bus Interface ................................................................................ Chip Select and Wait State Generation ...................................................... System Configuration and Protection ......................................................... Power Management .................................................................................... Parallel Input/Output Ports ......................................................................... Interrupt Inputs ........................................................................................... UART Module ................................................................................................ Timer Module ................................................................................................. Test Access Port.............................................................................................. System Design ................................................................................................... System Bus Configuration .............................................................................. MCF5272-Specific Features ............................................................................... Physical Layer Interface Controller (PLIC).................................................... Pulse-Width Modulation (PWM) Unit ........................................................... Queued Serial Peripheral Interface (QSPI)..................................................... Universal Serial Bus (USB) Module .............................................................. 1-1 1-4 1-4 1-5 1-5 1-5 1-5 1-6 1-6 1-6 1-6 1-7 1-7 1-7 1-7 1-8 1-8 1-8 1-8 1-9
Chapter 2 ColdFire Core
2.1 2.1.1 2.1.1.1 2.1.1.2 2.1.1.2.1 2.1.1.2.2 2.1.1.2.3 2.1.2 Features and Enhancements................................................................................ Decoupled Pipelines ....................................................................................... Instruction Fetch Pipeline (IFP).................................................................. Operand Execution Pipeline (OEP) ............................................................ Illegal Opcode Handling......................................................................... Hardware Multiply/Accumulate (MAC) Unit ........................................ Hardware Divide Unit............................................................................. Debug Module Enhancements ........................................................................ 2-1 2-1 2-2 2-3 2-3 2-3 2-4 2-4
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Paragraph Number 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.1.6 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.2.2.7 2.3 2.4 2.4.1 2.4.2 2.5 2.6 2.6.1 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 Title Page Number
Programming Model ........................................................................................... 2-5 User Programming Model .............................................................................. 2-6 Data Registers (D0-D7) ............................................................................. 2-6 Address Registers (A0-A6) ........................................................................ 2-6 Stack Pointer (A7, SP) ................................................................................ 2-7 Program Counter (PC) ................................................................................ 2-7 Condition Code Register (CCR) ................................................................. 2-7 MAC Programming Model......................................................................... 2-8 Supervisor Programming Model..................................................................... 2-8 Status Register (SR).................................................................................... 2-8 Vector Base Register (VBR) ...................................................................... 2-9 Cache Control Register (CACR) ................................................................ 2-9 Access Control Registers (ACR0-ACR1)................................................ 2-10 ROM Base Address Register (ROMBAR) ............................................... 2-10 RAM Base Address Register (RAMBAR) ............................................... 2-10 Module Base Address Register (MBAR) ................................................. 2-10 Integer Data Formats......................................................................................... 2-10 Organization of Data in Registers..................................................................... 2-10 Organization of Integer Data Formats in Registers ...................................... 2-11 Organization of Integer Data Formats in Memory ....................................... 2-12 Addressing Mode Summary ............................................................................. 2-12 Instruction Set Summary................................................................................... 2-13 Instruction Set Summary .............................................................................. 2-16 Instruction Timing ............................................................................................ 2-19 MOVE Instruction Execution Times ............................................................ 2-20 Execution Timings--One-Operand Instructions .......................................... 2-22 Execution Timings--Two-Operand Instructions.......................................... 2-23 Miscellaneous Instruction Execution Times................................................. 2-24 Branch Instruction Execution Times ............................................................ 2-25 Exception Processing Overview ....................................................................... 2-26 Exception Stack Frame Definition................................................................ 2-28 Processor Exceptions .................................................................................... 2-29
Chapter 3 Hardware Multiply/Accumulate (MAC) Unit
3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 Overview............................................................................................................. MAC Programming Model............................................................................. General Operation........................................................................................... MAC Instruction Set Summary ...................................................................... Data Representation........................................................................................ MAC Instruction Execution Timings.................................................................. 3-1 3-2 3-3 3-4 3-5 3-5
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Chapter 4 Local Memory
4.1 4.2 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 4.5 4.5.1 4.5.2 4.5.2.1 4.5.2.2 4.5.2.3 4.5.2.3.1 4.5.2.3.2 4.5.2.4 4.5.2.5 4.5.3 4.5.3.1 4.5.3.2 Interactions between Local Memory Modules ................................................... 4-1 Local Memory Registers..................................................................................... 4-2 SRAM Overview ................................................................................................ 4-2 SRAM Operation ............................................................................................ 4-2 SRAM Programming Model........................................................................... 4-2 SRAM Base Address Register (RAMBAR)............................................... 4-3 SRAM Initialization.................................................................................... 4-4 Programming RAMBAR for Power Management ..................................... 4-5 ROM Overview................................................................................................... 4-5 ROM Operation .............................................................................................. 4-5 ROM Programming Model............................................................................. 4-6 ROM Base Address Register (ROMBAR) ................................................. 4-6 Programming ROMBAR for Power Management ..................................... 4-7 Instruction Cache Overview ............................................................................... 4-7 Instruction Cache Physical Organization........................................................ 4-7 Instruction Cache Operation ........................................................................... 4-9 Interaction with Other Modules.................................................................. 4-9 Cache Coherency and Invalidation ............................................................. 4-9 Caching Modes ........................................................................................... 4-9 Cacheable Accesses .............................................................................. 4-10 Cache-Inhibited Accesses..................................................................... 4-10 Reset ......................................................................................................... 4-11 Cache Miss Fetch Algorithm/Line Fills ................................................... 4-11 Instruction Cache Programming Model........................................................ 4-12 Cache Control Register (CACR) .............................................................. 4-13 Access Control Registers (ACR0 and ACR1) .......................................... 4-15
Chapter 5 Debug Support
5.1 5.2 5.3 5.3.1 5.4 5.4.1 5.4.2 5.4.3 5.4.4 Overview............................................................................................................. Signal Description............................................................................................... Real-Time Trace Support.................................................................................... Begin Execution of Taken Branch (PST = 0x5) ............................................. Programming Model ........................................................................................... Revision A Shared Debug Resources ............................................................. Address Attribute Trigger Register (AATR) .................................................. Address Breakpoint Registers (ABLR, ABHR) ............................................. Configuration/Status Register (CSR).............................................................. 5-1 5-2 5-2 5-4 5-5 5-7 5-7 5-8 5-9
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Paragraph Number 5.4.5 5.4.6 5.4.7 5.5 5.5.1 5.5.2 5.5.2.1 5.5.2.2 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.2 5.5.3.3 5.5.3.3.1 5.5.3.3.2 5.5.3.3.3 5.5.3.3.4 5.5.3.3.5 5.5.3.3.6 5.5.3.3.7 5.5.3.3.8 5.5.3.3.9 5.5.3.3.10 5.5.3.3.11 5.5.3.3.12 5.6 5.6.1 5.6.1.1 5.6.2 5.7 5.7.1 5.7.2 5.8 Title Page Number 5-11 5-12 5-13 5-15 5-15 5-16 5-17 5-18 5-18 5-19 5-20 5-20 5-22 5-22 5-23 5-23 5-25 5-26 5-28 5-30 5-30 5-31 5-32 5-32 5-33 5-34 5-34 5-36 5-36 5-37 5-37 5-41 5-42
Data Breakpoint/Mask Registers (DBR, DBMR)......................................... Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... Trigger Definition Register (TDR) ............................................................... Background Debug Mode (BDM) .................................................................... CPU Halt....................................................................................................... BDM Serial Interface.................................................................................... Receive Packet Format ............................................................................. Transmit Packet Format............................................................................ BDM Command Set...................................................................................... ColdFire BDM Command Format............................................................ Extension Words as Required............................................................... Command Sequence Diagrams................................................................. Command Set Descriptions ...................................................................... Read A/D Register (rareg/rdreg) .......................................................... Write A/D Register (wareg/wdreg) ...................................................... Read Memory Location (read).............................................................. Write Memory Location (write) ........................................................... Dump Memory Block (dump) .............................................................. Fill Memory Block (fill) ....................................................................... Resume Execution (go) ........................................................................ No Operation (nop)............................................................................... Read Control Register (rcreg)............................................................... Write Control Register (wcreg) ............................................................ Read Debug Module Register (rdmreg) ............................................... Write Debug Module Register (wdmreg) ............................................. Real-Time Debug Support ................................................................................ Theory of Operation...................................................................................... Emulator Mode ......................................................................................... Concurrent BDM and Processor Operation .................................................. Processor Status, DDATA Definition............................................................... User Instruction Set ...................................................................................... Supervisor Instruction Set............................................................................. Motorola-Recommended BDM Pinout.............................................................
Chapter 6 System Integration Module (SIM)
6.1 6.2 6.2.1 6.2.2 6.2.3 Features ............................................................................................................... Programming Model ........................................................................................... SIM Register Memory Map............................................................................ Module Base Address Register (MBAR) ....................................................... System Configuration Register (SCR)............................................................ 6-1 6-3 6-3 6-4 6-5
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Paragraph Number 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.8.1 6.2.8.2 6.2.8.3 6.2.8.4 Title Page Number
System Protection Register (SPR) .................................................................. 6-6 Power Management Register (PMR).............................................................. 6-7 Activate Low-Power Register (ALPR)......................................................... 6-10 Device Identification Register (DIR)............................................................ 6-11 Software Watchdog Timer............................................................................ 6-12 Watchdog Reset Reference Register (WRRR) ......................................... 6-13 Watchdog Interrupt Reference Register (WIRR) ..................................... 6-13 Watchdog Counter Register (WCR) ......................................................... 6-14 Watchdog Event Register (WER)............................................................. 6-14
Chapter 7 Interrupt Controller
7.1 7.2 7.2.1 7.2.2 7.2.2.1 7.2.2.2 7.2.2.3 7.2.2.4 7.2.3 7.2.4 7.2.5 7.2.6 Overview............................................................................................................. Interrupt Controller Registers ............................................................................. Interrupt Controller Registers ......................................................................... Interrupt Control Registers (ICR1-ICR4) ...................................................... Interrupt Control Register 1 (ICR1) ........................................................... Interrupt Control Register 2 (ICR2) ........................................................... Interrupt Control Register 3 (ICR3) ........................................................... Interrupt Control Register 4 (ICR4) ........................................................... Interrupt Source Register (ISR) ...................................................................... Programmable Interrupt Transition Register (PITR)...................................... Programmable Interrupt Wakeup Register (PIWR)........................................ Programmable Interrupt Vector Register (PIVR) ........................................... 7-1 7-2 7-3 7-4 7-4 7-5 7-5 7-6 7-6 7-7 7-7 7-8
Chapter 8 Chip Select Module
8.1 8.1.1 8.1.2 8.1.3 8.2 8.2.1 8.2.2 Overview............................................................................................................. Features........................................................................................................... Chip Select Usage........................................................................................... Boot CS0 Operation........................................................................................ Chip Select Registers .......................................................................................... Chip Select Base Registers (CSBR0-CSBR7) ............................................... Chip Select Option Registers (CSOR0-CSOR7) ........................................... 8-1 8-1 8-1 8-2 8-2 8-3 8-5
Chapter 9 SDRAM Controller
9.1 9.2 Overview............................................................................................................. 9-1 SDRAM Controller Signals ................................................................................ 9-1
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Paragraph Number 9.3 9.4 9.5 9.5.1 9.5.2 9.6 9.7 9.8 9.9 9.10 9.10.1 9.10.2 9.10.3 Title Page Number
Interface to SDRAM Devices ............................................................................. 9-4 SDRAM Banks, Page Hits, and Page Misses ..................................................... 9-6 SDRAM Registers .............................................................................................. 9-6 SDRAM Configuration Register (SDCR) ...................................................... 9-6 SDRAM Timing Register (SDTR) ................................................................. 9-8 Auto Initialization ............................................................................................... 9-9 Power-Down and Self-Refresh ........................................................................... 9-9 Performance ...................................................................................................... 9-10 Solving Timing Issues with SDCR[INV] ......................................................... 9-13 SDRAM Interface ............................................................................................. 9-15 SDRAM Read Accesses ............................................................................... 9-16 SDRAM Write Accesses .............................................................................. 9-18 SDRAM Refresh Timing .............................................................................. 9-20
Chapter 10 DMA Controller
10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 DMA Data Transfer Types ............................................................................... DMA Address Modes ....................................................................................... DMA Controller Registers................................................................................ DMA Mode Register (DMR)........................................................................ DMA Interrupt Register (DIR) ..................................................................... DMA Source Address Register (DSAR) ...................................................... DMA Destination Address Register (DDAR) .............................................. DMA Byte Count Register (DBCR)............................................................. 10-1 10-2 10-2 10-2 10-4 10-5 10-6 10-6
Chapter 11 Ethernet Module
11.1 11.1.1 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 Overview........................................................................................................... Features......................................................................................................... Module Operation ............................................................................................. Transceiver Connection .................................................................................... FEC Frame Transmission ................................................................................. FEC Frame Reception................................................................................... CAM Interface .............................................................................................. Ethernet Address Recognition ...................................................................... Hash Table Algorithm .................................................................................. Interpacket Gap Time ................................................................................... Collision Handling........................................................................................ Internal and External Loopback.................................................................... Ethernet Error-Handling Procedure .............................................................. 11-1 11-1 11-2 11-3 11-4 11-5 11-7 11-7 11-8 11-9 11-9 11-9 11-9
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Paragraph Number 11.4.8.1 11.4.8.2 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 11.5.9 11.5.10 11.5.11 11.5.12 11.5.13 11.5.14 11.5.15 11.5.16 11.5.16.1 11.5.17 11.5.18 11.5.19 11.5.20 11.5.21 11.5.22 11.5.22.1 11.5.23 11.5.24 11.5.24.1 11.6 11.6.1 11.6.1.1 11.6.1.2 11.7 Title Page Number 11-10 11-10 11-11 11-12 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-22 11-23 11-24 11-25 11-26 11-27 11-27 11-28 11-28 11-29 11-30 11-30 11-30 11-31 11-31 11-32 11-32 11-33 11-34 11-36
Transmission Errors................................................................................ Reception Errors ..................................................................................... Programming Model ....................................................................................... Ethernet Control Register (ECR)................................................................ Interrupt Event Register (EIR).................................................................... Interrupt Mask Register (EIMR)................................................................. Interrupt Vector Status Register (IVSR)..................................................... Receive Descriptor Active Register (RDAR)............................................. Transmit Descriptor Active Register (TDAR)............................................ MII Management Frame Register (MMFR) ............................................... MII Speed Control Register (MSCR) ......................................................... FIFO Receive Bound Register (FRBR) ...................................................... FIFO Receive Start Register (FRSR).......................................................... Transmit FIFO Watermark (TFWR)........................................................... FIFO Transmit Start Register (TFSR) ........................................................ Receive Control Register (RCR) ................................................................ Maximum Frame Length Register (MFLR) ............................................... Transmit Control Register (TCR) ............................................................... RAM Perfect Match Address Low (MALR) .............................................. RAM Perfect Match Address High (MAUR) ......................................... Hash Table High (HTUR)........................................................................... Hash Table Low (HTLR)............................................................................ Pointer-to-Receive Descriptor Ring (ERDSR) ........................................... Pointer-to-Transmit Descriptor Ring (ETDSR).......................................... Receive Buffer Size Register (EMRBR) .................................................... Initialization Sequence................................................................................ Hardware Initialization ........................................................................... User Initialization (Prior to Asserting ETHER_EN) .................................. FEC Initialization........................................................................................ User Initialization (after setting ETHER_EN) ....................................... Buffer Descriptors........................................................................................... FEC Buffer Descriptor Tables .................................................................... Ethernet Receive Buffer Descriptor (RxBD).......................................... Ethernet Transmit Buffer Descriptor ...................................................... Differences between MCF5272 FEC and MPC860T FEC.............................
Chapter 12 Universal Serial Bus (USB)
12.1 12.2 12.2.1 Introduction....................................................................................................... 12-1 Module Operation ............................................................................................. 12-3 USB Module Architecture ............................................................................ 12-3
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Paragraph Number 12.2.1.1 12.2.1.2 12.2.1.3 12.2.1.4 12.2.1.5 12.3 12.3.1 12.3.2 12.3.2.1 12.3.2.2 12.3.2.3 12.3.2.4 12.3.2.5 12.3.2.6 12.3.2.7 12.3.2.8 12.3.2.9 12.3.2.10 12.3.2.11 12.3.2.12 12.3.2.13 12.3.2.14 12.3.2.15 12.3.2.16 12.3.2.17 12.3.2.18 12.3.2.19 12.3.3 12.3.3.1 12.3.3.2 12.3.4 12.3.4.1 12.3.4.2 12.3.4.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.4.1 12.4.4.1.1 12.4.4.1.2
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USB Transceiver Interface ....................................................................... 12-4 Clock Generator........................................................................................ 12-4 USB Control Logic ................................................................................... 12-4 Endpoint Controllers................................................................................. 12-5 USB Request Processor ............................................................................ 12-5 Register Description and Programming Model ................................................ 12-7 USB Memory Map........................................................................................ 12-7 Register Descriptions.................................................................................... 12-9 USB Frame Number Register (FNR) ....................................................... 12-9 USB Frame Number Match Register (FNMR)......................................... 12-9 USB Real-Time Frame Monitor Register (RFMR) ................................ 12-10 USB Real-Time Frame Monitor Match Register (RFMMR) ................. 12-10 USB Function Address Register (FAR) ................................................. 12-11 USB Alternate Settings Register (ASR) ................................................. 12-11 USB Device Request Data 1 and 2 Registers (DRR1/ 2) ....................... 12-12 USB Specification Number Register (SPECR) ...................................... 12-13 USB Endpoint 0 Status Register (EP0SR).............................................. 12-13 USB Endpoint 0 IN Configuration Register (IEP0CFG) ....................... 12-14 USB Endpoint 0 OUT Configuration Register (OEP0CFG) .................. 12-15 USB Endpoint 1-7 Configuration Register (EPnCFG) .......................... 12-16 USB Endpoint 0 Control Register (EP0CTL) ........................................ 12-16 USB Endpoint 1-7 Control Register (EPnCTL) .................................... 12-19 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0 Interrupt Registers (EP0ISR).............................................................. 12-20 USB Endpoints 1-7 Status / Interrupt Registers (EPnISR) .................... 12-23 USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR) ....................... 12-24 USB Endpoint 0-7 Data Registers (EPnDR).......................................... 12-25 USB Endpoint 0-7 Data Present Registers (EPnDPR)........................... 12-25 Configuration RAM.................................................................................... 12-26 Configuration RAM Content .................................................................. 12-26 USB Device Configuration Example...................................................... 12-27 USB Module Access Times........................................................................ 12-28 Registers ................................................................................................. 12-28 Endpoint FIFOs ...................................................................................... 12-28 Configuration RAM................................................................................ 12-28 Software Architecture and Application Notes ................................................ 12-28 USB Module Initialization.......................................................................... 12-28 USB Configuration and Interface Changes ................................................ 12-29 FIFO Configuration .................................................................................... 12-29 Data Flow.................................................................................................... 12-30 Control, Bulk, and Interrupt Endpoints .................................................. 12-30 IN Endpoints....................................................................................... 12-31 OUT Endpoints................................................................................... 12-31
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Paragraph Number 12.4.4.2 12.4.4.2.1 12.4.4.2.2 12.4.5 12.4.6 12.4.7 12.5 12.5.1 12.5.2 12.5.3 Title Page Number 12-31 12-32 12-32 12-32 12-33 12-33 12-34 12-34 12-34 12-35
Isochronous Endpoints............................................................................ IN Endpoints....................................................................................... OUT Endpoints................................................................................... Class- and Vendor-Specific Request Operation ......................................... remote wakeup and resume Operation........................................................ Endpoint Halt Feature................................................................................. Line Interface .................................................................................................. Attachment Detection ................................................................................. PCB Layout Recommendations.................................................................. Recommended USB Protection Circuit ......................................................
Chapter 13 Physical Layer Interface Controller (PLIC)
13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.3.1 13.2.3.2 13.2.3.3 13.2.3.4 13.2.3.5 13.2.4 13.2.4.1 13.2.4.2 13.2.4.3 13.2.5 13.2.5.1 13.2.5.2 13.2.5.3 13.3 13.3.1 13.3.2 13.3.3 13.4 13.5 13.5.1 13.5.2 13.5.3 13.5.4 Introduction....................................................................................................... 13-1 GCI/IDL Block ................................................................................................. 13-3 GCI/IDL B- and D-Channel Receive Data Registers ................................... 13-3 GCI/IDL B- and D-Channel Transmit Data Registers.................................. 13-4 GCI/IDL B- and D-Channel Bit Alignment ................................................. 13-5 B-Channel Unencoded Data ..................................................................... 13-5 B-Channel HDLC Encoded Data.............................................................. 13-6 D-Channel HDLC Encoded Data ............................................................. 13-7 D-Channel Unencoded Data ..................................................................... 13-7 GCI/IDL D-Channel Contention ............................................................. 13-8 GCI/IDL Looping Modes ............................................................................. 13-8 Automatic Echo Mode .............................................................................. 13-9 Local Loopback Mode .............................................................................. 13-9 Remote Loopback Mode........................................................................... 13-9 GCI/IDL Interrupts ..................................................................................... 13-10 GCI/IDL Periodic Frame Interrupt ......................................................... 13-10 GCI Aperiodic Status Interrupt.............................................................. 13-10 Interrupt Control ..................................................................................... 13-11 PLIC Timing Generator .................................................................................. 13-11 Clock Synthesis........................................................................................... 13-11 Super Frame Sync Generation .................................................................... 13-12 Frame Sync Synthesis................................................................................. 13-13 PLIC Register Memory Map .......................................................................... 13-14 PLIC Registers ................................................................................................ 13-15 B1 Data Receive Registers (P0B1RR-P3B1RR) ....................................... 13-15 B2 Data Receive Registers (P0B2RR-P3B2RR) ....................................... 13-16 D Data Receive Registers (P0DRR-P3DRR)............................................. 13-16 B1 Data Transmit Registers (P0B1TR-P3B1TR) ...................................... 13-17
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Paragraph Number 13.5.5 13.5.6 13.5.7 13.5.8 13.5.9 13.5.10 13.5.11 13.5.12 13.5.13 13.5.14 13.5.15 13.5.16 13.5.17 13.5.18 13.5.19 13.5.20 13.5.21 13.5.22 13.6 13.6.1 13.6.2 13.6.2.1 13.6.2.2 13.6.3 13.6.4 13.6.5 Title Page Number 13-17 13-18 13-19 13-20 13-21 13-22 13-24 13-24 13-25 13-26 13-27 13-28 13-29 13-29 13-30 13-31 13-32 13-32 13-33 13-33 13-34 13-34 13-35 13-36 13-39 13-40
B2 Data Transmit Registers (P0B2TR-P3B2TR) ...................................... D Data Transmit Registers (P0DTR-P3DTR)............................................ Port Configuration Registers (P0CR-P3CR).............................................. Loopback Control Register (PLCR) ........................................................... Interrupt Configuration Registers (P0ICR-P3ICR).................................... Periodic Status Registers (P0PSR-P3PSR) ................................................ Aperiodic Status Register (PASR).............................................................. GCI Monitor Channel Receive Registers (P0GMR-P3GMR) ................... GCI Monitor Channel Transmit Registers (P0GMT-P3GMT).................. GCI Monitor Channel Transmit Abort Register (PGMTA) ...................... GCI Monitor Channel Transmit Status Register (PGMTS)........................ GCI C/I Channel Receive Registers (P0GCIR-P3GCIR) .......................... GCI C/I Channel Transmit Registers (P0GCIT-P3GCIT) ......................... GCI C/I Channel Transmit Status Register (PGCITSR) ............................ D-Channel Status Register (PDCSR) ......................................................... D-Channel Request Register (PDRQR)...................................................... Sync Delay Registers (P0SDR-P3SDR) .................................................... Clock Select Register (PCSR) .................................................................... Application Examples..................................................................................... Introduction................................................................................................. PLIC Initialization ...................................................................................... Port Configuration Example ................................................................... Interrupt Configuration Example............................................................ Example 1: ISDN SOHO PBX with Ports 0, 1, 2, and 3 ............................ Example 2: ISDN SOHO PBX with Ports 1, 2, and 3 ................................ Example 3: Two-Line Remote Access with Ports 0 and 1 .........................
Chapter 14 Queued Serial Peripheral Interface (QSPI) Module
14.1 14.2 14.3 14.3.1 14.3.2 14.4 14.4.1 14.4.1.1 14.4.1.2 14.4.1.3 14.4.2 14.4.3 Overview........................................................................................................... Features ............................................................................................................. Module Description .......................................................................................... Interface and Pins.......................................................................................... Internal Bus Interface.................................................................................... Operation........................................................................................................... QSPI RAM.................................................................................................... Receive RAM ........................................................................................... Transmit RAM.......................................................................................... Command RAM........................................................................................ Baud Rate Selection...................................................................................... Transfer Delays............................................................................................. 14-1 14-1 14-1 14-2 14-3 14-3 14-4 14-5 14-6 14-6 14-6 14-7
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Paragraph Number 14.4.4 14.4.5 14.5 14.5.1 14.5.2 14.5.3 14.5.4 14.5.5 14.5.6 14.5.7 14.5.8 Title Page Number
Transfer Length............................................................................................. 14-8 Data Transfer ................................................................................................ 14-8 Programming Model ......................................................................................... 14-9 QSPI Mode Register (QMR) ........................................................................ 14-9 QSPI Delay Register (QDLYR) ................................................................. 14-11 QSPI Wrap Register (QWR)....................................................................... 14-12 QSPI Interrupt Register (QIR).................................................................... 14-12 QSPI Address Register (QAR) ................................................................... 14-14 QSPI Data Register (QDR)......................................................................... 14-14 Command RAM Registers (QCR0-QCR15).............................................. 14-14 Programming Example ............................................................................... 14-15
Chapter 15 Timer Module
15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 Overview........................................................................................................... Timer Operation................................................................................................ General-Purpose Timer Registers ..................................................................... Timer Mode Registers (TMR0-TMR3) ....................................................... Timer Reference Registers (TRR0-TRR3) .................................................. Timer Capture Registers (TCAP0-TCAP3) ................................................. Timer Counters (TCN0-TCN3).................................................................... Timer Event Registers (TER0-TER3).......................................................... 15-1 15-2 15-3 15-3 15-4 15-5 15-5 15-5
Chapter 16 UART Modules
16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.3.9 16.3.10 16.3.11 16.3.12 Overview........................................................................................................... 16-1 Serial Module Overview ................................................................................... 16-2 Register Descriptions ........................................................................................ 16-3 UART Mode Registers 1 (UMR1n).............................................................. 16-5 UART Mode Register 2 (UMR2n) ............................................................... 16-6 UART Status Registers (USRn) ................................................................... 16-7 UART Clock-Select Registers (UCSRn)...................................................... 16-8 UART Command Registers (UCRn) ............................................................ 16-9 UART Receiver Buffers (URBn) ............................................................... 16-11 UART Transmitter Buffers (UTBn) ........................................................... 16-11 UART Input Port Change Registers (UIPCRn).......................................... 16-12 UART Auxiliary Control Registers (UACRn) ........................................... 16-12 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 16-13 UART Divider Upper/Lower Registers (UDUn/UDLn) ............................ 16-14 UART Autobaud Registers (UABUn/UABLn).......................................... 16-15
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Paragraph Number 16.3.13 16.3.14 16.3.15 16.3.16 16.3.17 16.4 16.5 16.5.1 16.5.1.1 16.5.1.2 16.5.1.2.1 16.5.1.2.2 16.5.1.2.3 16.5.2 16.5.2.1 16.5.2.2 16.5.2.3 16.5.2.4 16.5.3 16.5.3.1 16.5.3.2 16.5.3.3 16.5.4 16.5.5 16.5.5.1 16.5.5.2 16.5.5.3 16.5.6 16.5.6.1 Title Page Number 16-15 16-16 16-17 16-18 16-18 16-19 16-20 16-20 16-20 16-21 16-21 16-22 16-22 16-23 16-23 16-25 16-26 16-26 16-28 16-28 16-28 16-29 16-29 16-31 16-31 16-31 16-31 16-31 16-32
UART Transmitter FIFO Registers (UTFn) ............................................... UART Receiver FIFO Registers (URFn) ................................................... UART Fractional Precision Divider Control Registers (UFPDn) .............. UART Input Port Registers (UIPn) ............................................................ UART Output Port Command Registers (UOP1n/UOP0n) ....................... UART Module Signal Definitions .................................................................. Operation......................................................................................................... Transmitter/Receiver Clock Source............................................................ Programmable Divider............................................................................ Calculating Baud Rates........................................................................... CLKIN Baud Rates............................................................................. External Clock .................................................................................... Autobaud Detection ............................................................................ Transmitter and Receiver Operating Modes............................................... Transmitting ........................................................................................... Receiver .................................................................................................. Transmitter FIFO .................................................................................... Receiver FIFO ....................................................................................... Looping Modes ........................................................................................... Automatic Echo Mode ............................................................................ Local Loop-Back Mode .......................................................................... Remote Loop-Back Mode....................................................................... Multidrop Mode.......................................................................................... Bus Operation ............................................................................................. Read Cycles ............................................................................................ Write Cycles ........................................................................................... Interrupt Acknowledge Cycles ............................................................... Programming .............................................................................................. UART Module Initialization Sequence ..................................................
Chapter 17 General Purpose I/O Module
17.1 17.2 17.2.1 17.2.2 17.2.3 17.2.4 17.3 17.3.1 17.3.2 Overview........................................................................................................... 17-1 Port Control Registers....................................................................................... 17-2 Port A Control Register (PACNT)................................................................ 17-2 Port B Control Register (PBCNT) ................................................................ 17-5 Port C Control Register................................................................................. 17-8 Port D Control Register (PDCNT)................................................................ 17-8 Data Direction Registers ................................................................................... 17-9 Port A Data Direction Register (PADDR).................................................. 17-10 Port B Data Direction Register (PBDDR) .................................................. 17-10
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Paragraph Number 17.3.3 17.4 17.4.1 Title Page Number
Port C Data Direction Register (PCDDR) .................................................. 17-11 Port Data Registers ......................................................................................... 17-11 Port Data Register (PxDAT)....................................................................... 17-11
Chapter 18 Pulse Width Modulation (PWM) Module
18.1 18.2 18.3 18.3.1 18.3.2 Overview........................................................................................................... PWM Operation ................................................................................................ PWM Programming Model............................................................................... PWM Control Register (PWCRn) ................................................................ PWM Width Register (PWWDn) ................................................................. 18-1 18-2 18-2 18-3 18-4
Chapter 19 Signal Descriptions
19.1 19.2 19.3 19.4 19.4.1 19.5 19.6 19.6.1 19.6.2 19.6.3 19.6.4 19.6.5 19.6.6 19.6.7 19.6.8 19.6.9 19.6.10 19.6.11 19.6.12 19.6.13 19.7 19.7.1 19.7.2 19.7.3 19.7.4 19.8 MCF5272 Block Diagram with Signal Interfaces ............................................ 19-1 Signal List ......................................................................................................... 19-2 Address Bus (A[22:0]/SDA[13:0]) ................................................................. 19-18 Data Bus (D[31:0]) ......................................................................................... 19-18 Dynamic Data Bus Sizing........................................................................... 19-18 Chip Selects (CS7/SDCS, CS[6:0]) ................................................................ 19-19 Bus Control Signals ........................................................................................ 19-19 Output Enable/Read (OE/RD) .................................................................... 19-19 Byte Strobes (BS[3:0])................................................................................ 19-19 Read/Write (R/W)....................................................................................... 19-21 Transfer Acknowledge (TA/PB5)............................................................... 19-21 Hi-Z............................................................................................................. 19-21 Bypass......................................................................................................... 19-22 SDRAM Row Address Strobe (RAS0)....................................................... 19-22 SDRAM Column Address Strobe (CAS0) ................................................. 19-22 SDRAM Clock (SDCLK)........................................................................... 19-22 SDRAM Write Enable (SDWE) ................................................................. 19-22 SDRAM Clock Enable (SDCLKE) ............................................................ 19-22 SDRAM Bank Selects (SDBA[1:0]) .......................................................... 19-22 SDRAM Row Address 10 (A10)/A10 Precharge (A10_PRECHG)........... 19-22 CPU Clock and Reset Signals......................................................................... 19-22 RSTI............................................................................................................ 19-22 DRESETEN ................................................................................................ 19-23 CPU External Clock (CLKIN).................................................................... 19-23 Reset Output (RSTO).................................................................................. 19-23 Interrupt Request Inputs (INT[6:1])................................................................ 19-23
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Paragraph Number 19.9 19.10 19.10.1 19.10.2 19.10.3 19.10.4 19.10.5 19.11 19.11.1 19.11.2 19.11.3 19.11.4 19.11.5 19.11.6 19.11.7 19.11.8 19.11.9 19.11.10 19.12 19.12.1 19.12.2 19.12.3 19.12.4 19.13 19.13.1 19.13.2 19.13.3 19.13.4 19.13.5 19.13.6 19.13.7 19.13.8 19.13.9 19.13.10 19.13.11 19.13.12 19.13.13 19.13.14 19.14 19.15 19.15.1 19.15.2 19.15.3
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Page Number 19-23 19-24 19-24 19-24 19-24 19-25 19-25 19-25 19-25 19-25 19-25 19-25 19-25 19-26 19-26 19-26 19-26 19-26 19-27 19-27 19-27 19-27 19-27 19-27 19-27 19-27 19-28 19-28 19-28 19-28 19-28 19-28 19-28 19-29 19-29 19-29 19-29 19-29 19-29 19-30 19-30 19-30 19-30
General-Purpose I/O (GPIO) Ports ................................................................. UART0 Module Signals and PB[4:0] ............................................................. Transmit Serial Data Output (URT0_TxD/PB0) ........................................ Receive Serial Data Input (URT0_RxD/PB1) ............................................ Clear-to-Send (URT0_CTS/PB2) ............................................................... Request to Send (URT0_RTS/PB3) ............................................................ Clock (URT0_CLK/PB4) ........................................................................... USB Module Signals and PA[6:0].................................................................. USB Transmit Serial Data Output (USB_TP/PA0).................................... USB Receive Serial Data Input (USB_RP/PA1)........................................ USB Receive Data Negative (USB_RN/PA2)............................................ USB Transmit Data Negative (USB_TN/PA3) .......................................... USB Suspend Driver (USB_SUSP/PA4) ................................................... USB Transmitter Output Enable (USB_TxEN/PA5) ................................. USB Rx Data Output (USB_RxD/PA6) ..................................................... USB_D+ and USB_D-................................................................................ USB_CLK................................................................................................... INT1/USB Wake-on-Ring (USB_WOR) ................................................... Timer Module Signals..................................................................................... Timer Input 0 (TIN0).................................................................................. Timer Output (TOUT0)/PB7 ...................................................................... Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2) .................... Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1).............. Ethernet Module Signals................................................................................. Transmit Clock (E_TxCLK)....................................................................... Transmit Data (E_TxD0) ............................................................................ Collision (E_COL)...................................................................................... Receive Data Valid (E_RxDV)................................................................... Receive Clock (E_RxCLK) ........................................................................ Receive Data (E_RxD0) ............................................................................. Transmit Enable (E_TxEN) ........................................................................ Transmit Data (E_TxD[3:1]/PB[10:8]) ...................................................... Receive Data (E_RxD[3:1]/PB[13:11])...................................................... Receive Error (E_RxER/PB14) .................................................................. Management Data Clock (E_MDC/PB15) ................................................. Management Data (E_MDIO) .................................................................... Transmit Error (E_TxER)........................................................................... Carrier Receive Sense (E_CRS) ................................................................. PWM Module Signals (PWM_OUT0-PWM_OUT2]) .................................. Queued Serial Peripheral Interface (QSPI) Signals ........................................ QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL)..................... QSPI Synchronous Serial Data Input (QSPI_Din) ..................................... QSPI Serial Clock (QSPI_CLK/BUSW1)..................................................
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Paragraph Number 19.15.4 19.15.5 19.15.6 19.15.7 19.16 19.16.1 19.16.1.1 19.16.1.2 19.16.1.3 19.16.1.4 19.16.1.5 19.16.1.6 19.16.1.7 19.16.1.8 19.16.1.9 19.16.2 19.16.2.1 19.16.2.2 19.16.2.3 19.16.2.4 19.16.2.5 19.16.2.6 19.16.3 19.16.3.1 19.16.3.2 19.16.3.3 19.16.3.4 19.17 19.17.1 19.17.2 19.17.3 19.17.4 19.17.5 19.17.6 19.17.7 19.17.8 19.17.9 19.17.10 19.18 19.19 Title Page Number 19-30 19-31 19-31 19-31 19-31 19-31 19-31 19-32 19-32 19-32 19-32 19-32 19-32 19-33 19-33 19-33 19-33 19-33 19-34 19-34 19-34 19-34 19-34 19-35 19-35 19-35 19-36 19-36 19-36 19-36 19-37 19-37 19-37 19-37 19-37 19-37 19-38 19-38 19-38 19-39
Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0).................... Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................ Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............. Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3)............ Physical Layer Interface Controller TDM Ports and UART 1 ....................... GCI/IDL TDM Port 0. ................................................................................ Frame Sync (FSR0/FSC0/PA8).............................................................. D-Channel Grant (DGNT0/PA9)............................................................ Data Clock (DCL0/URT1_CLK) ........................................................... Serial Data Input (DIN0/URT1_RxD).................................................... UART1 CTS (URT1_CTS/QSPI_CS2) ................................................. UART1 RTS (URT1_RTS/INT5)........................................................... Serial Data Output (DOUT0/URT1_TxD) ............................................. D-Channel Request(DREQ0/PA10) ....................................................... QSPI Chip Select 1 (QSPI_CS1/PA11).................................................. GCI/IDL TDM Port 1 ................................................................................. GCI/IDL Data Clock (DCL1/GDCL1_OUT)......................................... GCI/IDL Data Out (DOUT1) ................................................................. GCI/IDL Data In (DIN1) ........................................................................ GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ......................................... D-Channel Request (DREQ1/PA14) ...................................................... D-Channel Grant (DGNT1_INT6/PA15_INT6) .................................... GCI/IDL TDM Ports 2 and 3...................................................................... GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) .................................. GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13) .................................. QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7 (PA7/DOUT3/QSPI_CS3).................................................................. INT4 and Port 3 GCI/IDL Data In (INT4/DIN3) ................................... JTAG Test Access Port and BDM Debug Port............................................... Test Clock (TCK/PSTCLK) ....................................................................... Test Mode Select and Force Breakpoint (TMS/BKPT).............................. Test and Debug Data Out (TDO/DSO)....................................................... Test and Debug Data In (TDI/DSI) ............................................................ JTAG TRST and BDM Data Clock (TRST/DSCLK) ................................ Motorola Test Mode Select (MTMOD)...................................................... Debug Transfer Error Acknowledge (TEA) ............................................... Processor Status Outputs (PST[3:0]) .......................................................... Debug Data (DDATA[3:0])........................................................................ Device Test Enable (TEST)........................................................................ Operating Mode Configuration Pins............................................................... Power Supply Pins ..........................................................................................
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Chapter 20 Bus Operation
20.1 20.2 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.3 20.4 20.5 20.5.1 20.6 20.6.1 20.6.2 20.7 20.8 20.9 20.10 20.11 20.12 20.12.1 20.12.2 20.12.3 20.12.4 Features ............................................................................................................. 20-1 Bus and Control Signals.................................................................................... 20-1 Address Bus (A[22:0]).................................................................................. 20-2 Data Bus (D[31:0]) ....................................................................................... 20-2 Read/Write (R/W)......................................................................................... 20-2 Transfer Acknowledge (TA)......................................................................... 20-3 Transfer Error Acknowledge (TEA)............................................................. 20-3 Bus Exception: Double Bus Fault..................................................................... 20-4 Bus Characteristics............................................................................................ 20-4 Data Transfer Mechanism................................................................................. 20-4 Bus Sizing ..................................................................................................... 20-5 External Bus Interface Types............................................................................ 20-8 Interface for FLASH/SRAM Devices with Byte Strobes............................. 20-8 Interface for FLASH/SRAM Devices without Byte Strobes...................... 20-13 Burst Data Transfers ....................................................................................... 20-18 Misaligned Operands ...................................................................................... 20-18 Interrupt Cycles............................................................................................... 20-19 Bus Errors ....................................................................................................... 20-20 Bus Arbitration................................................................................................ 20-22 Reset Operation............................................................................................... 20-22 Master Reset ............................................................................................... 20-23 Normal Reset .............................................................................................. 20-24 Software Watchdog Timer Reset Operation............................................... 20-25 Soft Reset Operation................................................................................... 20-26
Chapter 21 IEEE 1149.1 Test Access Port (JTAG)
21.1 21.2 21.3 21.4 21.5 21.6 21.7 Overview........................................................................................................... JTAG Test Access Port and BDM Debug Port................................................. TAP Controller.................................................................................................. Boundary Scan Register.................................................................................... Instruction Register........................................................................................... Restrictions ....................................................................................................... Non-IEEE 1149.1 Operation............................................................................. 21-1 21-2 21-3 21-4 21-7 21-8 21-9
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Chapter 22 Mechanical Data
22.1 22.2 Pinout ................................................................................................................ 22-1 Package Dimensions ......................................................................................... 22-2
Chapter 23 Electrical Characteristics
23.1 23.1.1 23.1.2 23.1.3 23.2 23.2.1 23.3 23.3.1 23.3.2 23.3.3 23.4 23.5 23.6 23.6.1 23.6.2 23.6.3 23.6.4 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 Maximum Ratings............................................................................................. 23-1 Supply, Input Voltage, and Storage Temperature......................................... 23-1 Operating Temperature ................................................................................. 23-2 Resistance ..................................................................................................... 23-2 DC Electrical Specifications ............................................................................. 23-3 Output Driver Capability and Loading ......................................................... 23-3 AC Electrical Specifications ............................................................................. 23-5 Clock Input and Output Timing Specifications ............................................ 23-5 Processor Bus Input Timing Specifications.................................................. 23-6 Processor Bus Output Timing Specifications ............................................... 23-7 Debug AC Timing Specifications................................................................... 23-12 SDRAM Interface Timing Specifications....................................................... 23-13 Fast Ethernet AC Timing Specifications ........................................................ 23-15 MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER, and E_RxCLK).............................................................................................. 23-15 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER, E_TxCLK) .............................................................................................. 23-16 MII Async Inputs Signal Timing (CRS and COL) ..................................... 23-17 MII Serial Management Channel Timing (MDIO and MDC).................... 23-17 Timer Module AC Timing Specifications ...................................................... 23-18 UART Modules AC Timing Specifications.................................................... 23-19 PLIC Module: IDL and GCI Interface Timing Specifications ....................... 23-20 General-Purpose I/O Port AC Timing Specifications..................................... 23-25 USB Interface AC Timing Specifications....................................................... 23-25 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 23-26 QSPI Electrical Specifications........................................................................ 23-27 PWM Electrical Specifications ....................................................................... 23-28
Appendix A List of Memory Maps
A.1 List of Memory Map Tables .............................................................................. A-1
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Appendix B Buffering and Impedance Matching Index
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Figure Number Title Page Number
1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 4-1 4-2 4-3 4-4 4-5 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-18 5-17
MCF5272 Block Diagram............................................................................................. 1-2 ColdFire Pipeline .......................................................................................................... 2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-4 ColdFire Programming Model...................................................................................... 2-6 Condition Code Register (CCR) ................................................................................... 2-7 Status Register (SR)...................................................................................................... 2-9 Vector Base Register (VBR)......................................................................................... 2-9 Organization of Integer Data Formats in Data Registers............................................ 2-11 Organization of Integer Data Formats in Address Registers ...................................... 2-11 Memory Operand Addressing..................................................................................... 2-12 Exception Stack Frame Form...................................................................................... 2-28 ColdFire MAC Multiplication and Accumulation........................................................ 3-2 MAC Programming Model ........................................................................................... 3-2 SRAM Base Address Register (RAMBAR) ................................................................. 4-3 ROM Base Address Register (ROMBAR) .................................................................. 4-6 Instruction Cache Block Diagram................................................................................. 4-8 Cache Control Register (CACR) ................................................................................ 4-13 Access Control Register Format (ACRn) ................................................................... 4-15 Processor/Debug Module Interface............................................................................... 5-1 PSTCLK Timing........................................................................................................... 5-2 Example JMP Instruction Output on PST/DDATA...................................................... 5-5 Debug Programming Model ......................................................................................... 5-6 Address Attribute Trigger Register (AATR) ................................................................ 5-7 Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9 Configuration/Status Register (CSR).......................................................................... 5-10 Data Breakpoint/Mask Registers (DBR and DBMR)................................................. 5-12 Program Counter Breakpoint Register (PBR)............................................................. 5-13 Program Counter Breakpoint Mask Register (PBMR) ............................................... 5-13 Trigger Definition Register (TDR) ............................................................................. 5-14 BDM Serial Interface Timing ..................................................................................... 5-17 Receive BDM Packet.................................................................................................. 5-17 Transmit BDM Packet ................................................................................................ 5-18 BDM Command Format ............................................................................................. 5-20 Command Sequence Diagram..................................................................................... 5-21 RAREG/RDREG Command Sequence............................................................................ 5-22 RAREG/RDREG Command Format ............................................................................... 5-22
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Figure Page Title Number Number 5-20 WAREG/WDREG Command Sequence .......................................................................... 5-23 WAREG/WDREG Command Format.............................................................................. 5-23 5-19 READ Command Sequence.......................................................................................... 5-24 5-22 READ Command/Result Formats................................................................................. 5-24 5-21 WRITE Command Format ............................................................................................ 5-25 5-23 WRITE Command Sequence ........................................................................................ 5-26 5-24 DUMP Command/Result Formats ............................................................................... 5-27 5-25 DUMP Command Sequence ......................................................................................... 5-28 5-26 FILL Command Sequence............................................................................................ 5-29 5-28 FILL Command Format............................................................................................... 5-29 5-27 GO Command Sequence.............................................................................................. 5-30 5-30 NOP Command Sequence ............................................................................................ 5-30 5-32 GO Command Format.................................................................................................. 5-30 5-29 NOP Command Format................................................................................................ 5-30 5-31 RCREG Command Sequence........................................................................................ 5-31 5-34 RCREG Command/Result Formats............................................................................... 5-31 5-33 WCREG Command Sequence ....................................................................................... 5-32 5-36 WCREG Command/Result Formats.............................................................................. 5-32 5-35 RDMREG Command Sequence..................................................................................... 5-33 5-38 RDMREG BDM Command/Result Formats .................................................................. 5-33 5-37 WDMREG BDM Command Format.............................................................................. 5-33 5-39 WDMREG Command Sequence .................................................................................... 5-34 5-40 5-41 Recommended BDM Connector................................................................................. 5-42 6-1 SIM Block Diagram...................................................................................................... 6-1 6-2 Module Base Address Register (MBAR) ..................................................................... 6-4 6-3 System Configuration Register (SCR).......................................................................... 6-5 6-4 System Protection Register (SPR) ................................................................................ 6-6 6-5 Power Management Register (PMR) ............................................................................ 6-8 6-6 Activate Low-Power Register (ALPR)....................................................................... 6-10 6-7 Device Identification Register (DIR).......................................................................... 6-12 6-8 Watchdog Reset Reference Register (WRRR) ........................................................... 6-13 6-9 Watchdog Interrupt Reference Register (WIRR) ....................................................... 6-13 6-10 Watchdog Counter Register (WCR) ........................................................................... 6-14 6-11 Watchdog Event Register (WER)............................................................................... 6-14 7-1 Interrupt Controller Block Diagram.............................................................................. 7-2 7-2 Interrupt Control Register 1 (ICR1).............................................................................. 7-4 7-3 Interrupt Control Register 2 (ICR2).............................................................................. 7-5 7-4 Interrupt Control Register 3 (ICR3).............................................................................. 7-5 7-5 Interrupt Control Register 4(ICR4)............................................................................... 7-6 7-6 Interrupt Source Register (ISR) .................................................................................... 7-6 7-7 Programmable Interrupt Transition Register (PITR).................................................... 7-7 7-8 Programmable Interrupt Wakeup Register (PIWR)...................................................... 7-8 7-9 Programmable Interrupt Vector Register (PIVR) ......................................................... 7-9
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Figure Number 8-1 8-2 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 10-1 10-2 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 Title Page Number
Chip Select Base Registers (CSBRn) ........................................................................... 8-3 Chip Select Option Registers (CSORn)....................................................................... 8-5 SDRAM Controller Signals .......................................................................................... 9-2 54-Pin TSOP SDRAM Pin Definition .......................................................................... 9-3 SDRAM Configuration Register (SDCR) .................................................................... 9-6 SDRAM Timing Register (SDTR) ............................................................................... 9-8 Example Setup Time Violation on SDRAM Data Input during Write....................... 9-13 Timing Refinement with Inverted SDCLK................................................................. 9-13 Timing Refinement with True CAS Latency and Inverted SDCLK........................... 9-14 Timing Refinement with Effective CAS Latency....................................................... 9-14 SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1 ............................... 9-17 SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1 .................................. 9-18 SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 .............................. 9-19 SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 ................................. 9-20 SDRAM Refresh Cycle............................................................................................... 9-21 Enter SDRAM Self-Refresh Mode ............................................................................. 9-22 Exit SDRAM Self-Refresh Mode ............................................................................... 9-23 DMA Mode Register (DMR)...................................................................................... 10-2 DMA Interrupt Register (DIR) ................................................................................... 10-4 DMA Source Address Register (DSAR) .................................................................... 10-6 DMA Destination Address Register (DDAR) ............................................................ 10-6 DMA Byte Count Register (DBCR) ........................................................................... 10-6 Ethernet Block Diagram ............................................................................................. 11-2 Fast Ethernet Module Block Diagram ........................................................................ 11-2 Ethernet Frame Format ............................................................................................... 11-4 Ethernet Address Recognition Flowchart ................................................................... 11-8 Ethernet Control Register (ECR) .............................................................................. 11-12 EIMR Register ......................................................................................................... 11-14 Interrupt Vector Status Register (IVSR)................................................................... 11-14 RDAR Register ......................................................................................................... 11-15 TDAR Register ......................................................................................................... 11-16 MII Management Frame Register (MMFR) ............................................................. 11-17 MII Speed Control Register (MSCR) ...................................................................... 11-18 FIFO Receive Bound Register (FRBR) ................................................................... 11-20 FIFO Receive Start Register (FRSR)....................................................................... 11-20 Transmit FIFO Watermark (TFWR)........................................................................ 11-21 FIFO Transmit Start Register (TFSR) ...................................................................... 11-22 Receive Control Register (RCR) .............................................................................. 11-23 Maximum Frame Length Register (MFLR) ............................................................. 11-24 Transmit Control Register (TCR) ............................................................................. 11-25 RAM Perfect Match Address Low (MALR) ............................................................ 11-26 RAM Perfect Match Address High (MAUR) ........................................................... 11-26 Hash Table High (HTUR)........................................................................................ 11-27
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Figure Page Title Number Number 11-22 Hash Table Low (HTLR)......................................................................................... 11-27 11-23 Pointer to Receive Descriptor Ring (ERDSR).......................................................... 11-28 11-24 Pointer to Transmit Descriptor Ring (ETDSR) ........................................................ 11-29 11-25 Receive Buffer Size (EMRBR)................................................................................. 11-29 11-26 Receive Buffer Descriptor (RxBD) .......................................................................... 11-33 11-27 Transmit Buffer Descriptor (TxBD) ........................................................................ 11-34 12-1 The USB "tiered star" topology.................................................................................. 12-2 12-2 USB Module Block Diagram...................................................................................... 12-3 12-3 USB Frame Number Register (FNR).......................................................................... 12-9 12-4 USB Frame Number Match Register (FNMR)........................................................... 12-9 12-5 USB Real-Time Frame Monitor Register (RFMR) .................................................. 12-10 12-6 USB Real-Time Frame Monitor Match Register (RFMMR) ................................... 12-11 12-7 USB Function Address Register (FAR).................................................................... 12-11 12-8 USB Alternate Settings Register (ASR) ................................................................... 12-12 12-9 USB Device Request Data 1 Register (DRR1)......................................................... 12-12 12-10 USB Device Request Data 2 Register (DRR2)......................................................... 12-13 12-11 USB Specification Number Register (SPECR) ........................................................ 12-13 12-12 USB Endpoint 0 Status Register (EP0SR)................................................................ 12-14 12-13 USB Endpoint 0 IN Configuration Register (IEP0CFG).......................................... 12-15 12-14 USB Endpoint 0 OUT Configuration Register ......................................................... 12-15 12-15 USB Endpoint 1-7 Configuration Register .............................................................. 12-16 12-16 USB Endpoint 0 Control Register (EP0CTL)........................................................... 12-16 12-17 USB Endpoint 1-7 Control Register (EPnCTL) ....................................................... 12-19 12-18 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0 Interrupt Registers (EP0ISR) .................................................................................... 12-21 12-19 USB Endpoints 1-7 Interrupt Status Registers (EPnISR) ........................................ 12-23 12-20 USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR) .......................................... 12-24 12-22 USB Endpoint 0-7 Data Present Registers (EPnDPR) ............................................. 12-25 12-21 USB Endpoint 0-7 Data Registers (EPnDR) ............................................................ 12-25 12-23 Example USB Configuration Descriptor Structure................................................... 12-27 12-24 Recommended USB Line Interface .......................................................................... 12-34 12-25 USB Protection Circuit ............................................................................................. 12-36 13-1 PLIC System Diagram ................................................................................................ 13-2 13-2 GCI/IDL Receive Data Flow ...................................................................................... 13-3 13-3 GCI/IDL B-Channel Receive Data Register Demultiplexing..................................... 13-4 13-4 GCI/IDL Transmit Data Flow..................................................................................... 13-4 13-5 GCI/IDL B Data Transmit Register Multiplexing ...................................................... 13-5 13-6 B-Channel Unencoded and HDLC Encoded Data...................................................... 13-6 13-7 D-Channel HDLC Encoded and Unencoded Data...................................................... 13-7 13-8 D-Channel Contention ................................................................................................ 13-8 13-9 GCI/IDL Loopback Mode........................................................................................... 13-9 13-10 Periodic Frame Interrupt ........................................................................................... 13-10 13-11 PLIC Internal Timing Signal Routing....................................................................... 13-13
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Figure Number 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 13-28 13-29 13-30 13-31 13-32 13-33 13-34 13-35 13-36 13-37 13-38 13-39 13-40 13-41 13-42 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 15-1 15-2 Title Page Number
PLIC Clock Generator .............................................................................................. 13-13 B1 Receive Data Registers P0B1RR-P3B1RR ........................................................ 13-16 B2 Receive Data Registers P0B2RR - P3B2RR ...................................................... 13-16 D Receive Data Registers P0DRR-P3DRR ............................................................. 13-17 B1 Transmit Data Registers P0B1TR-P3B1TR ....................................................... 13-17 B2 Transmit Data Registers P0B2TR-P3B2TR ....................................................... 13-18 D Transmit Data Registers P0DTR-P3DTR ............................................................ 13-18 Port Configuration Registers (P0CR-P3CR)............................................................ 13-19 Loopback Control Register (PLCR) ......................................................................... 13-20 Interrupt Configuration Registers (P0ICR-P3ICR).................................................. 13-21 Periodic Status Registers (P0PSR-P3PSR) .............................................................. 13-22 Aperiodic Status Register (PASR)............................................................................ 13-24 GCI Monitor Channel Receive Registers (P0GMR-P3GMR) ................................. 13-25 GCI Monitor Channel Transmit Registers (P0GMT-P3GMT) ................................ 13-26 GCI Monitor Channel Transmit Abort Register (PGMTA) ..................................... 13-26 GCI Monitor Channel Transmit Status Register (PGMTS)...................................... 13-27 GCI C/I Channel Receive Registers (P0GCIR-P3GCIR) ........................................ 13-28 GCI C/I Channel Transmit Registers (P0GCIT-P3GCIT) ....................................... 13-29 GCI C/I Channel Transmit Status Register (PGCITSR)........................................... 13-30 D-Channel Status Register (PDCSR)........................................................................ 13-30 D-Channel Request Registers (PDRQR) .................................................................. 13-31 Sync Delay Registers (P0SDR-P3SDR) .................................................................. 13-32 Clock Select Register (PCSR) .................................................................................. 13-33 Port 1 Configuration Register (P1CR)...................................................................... 13-35 Port 1 Interrupt Configuration Register (P1ICR)...................................................... 13-36 ISDN SOHO PABX Example .................................................................................. 13-37 Standard IDL2 10-Bit Mode ..................................................................................... 13-38 ISDN SOHO PABX Example .................................................................................. 13-39 Standard IDL2 10-bit mode. ..................................................................................... 13-40 Two-Line Remote Access......................................................................................... 13-41 Standard IDL2 8-Bit mode........................................................................................ 13-41 QSPI Block Diagram .................................................................................................. 14-2 QSPI RAM Model ...................................................................................................... 14-5 QSPI Mode Register (QMR) ...................................................................................... 14-9 QSPI Clocking and Data Transfer Example ............................................................. 14-11 QSPI Delay Register (QDLYR)................................................................................ 14-11 QSPI Wrap Register (QWR)..................................................................................... 14-12 QSPI Interrupt Register (QIR) .................................................................................. 14-12 QSPI Address Register ............................................................................................. 14-14 QSPI Data Register ................................................................................................... 14-14 Command RAM Registers (QCR0-QCR15)............................................................ 14-15 Timer Block Diagram ................................................................................................. 15-2 Timer Mode Registers (TMR0-TMR3)...................................................................... 15-3
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Figure Page Title Number Number 15-3 Timer Reference Registers (TRR0-TRR3) ................................................................ 15-4 15-4 Timer Capture Registers (TCAP0-TCAP3) ............................................................... 15-5 15-5 Timer Counter (TCN0-TCN3) ................................................................................... 15-5 15-6 Timer Event Registers (TER0-TER3)........................................................................ 15-5 16-1 Simplified Block Diagram .......................................................................................... 16-1 16-2 UART Mode Registers 1 (UMR1n)............................................................................ 16-5 16-3 UART Mode Register 2 (UMR2n) ............................................................................. 16-6 16-4 UART Status Registers (USRn).................................................................................. 16-7 16-5 UART Clock-Select Registers (UCSRn) .................................................................... 16-9 16-6 UART Command Registers (UCRn) .......................................................................... 16-9 16-7 UART Receiver Buffer (URBn) ............................................................................... 16-11 16-8 UART Transmitter Buffers (UTBn) ......................................................................... 16-12 16-9 UART Input Port Change Registers (UIPCRn) ........................................................ 16-12 16-10 UART Auxiliary Control Registers (UACRn) ......................................................... 16-13 16-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 16-13 16-12 UART Divider Upper Registers (UDUn) ................................................................. 16-14 16-13 UART Divider Lower Registers (UDLn) ................................................................. 16-15 16-14 UART Autobaud Upper Registers (UABUn) ........................................................... 16-15 16-15 UART Autobaud Lower Registers (UABLn) ........................................................... 16-15 16-16 UART Transmitter FIFO Registers (UTFn) ............................................................. 16-16 16-17 UART Receiver FIFO Registers (URFn) ................................................................. 16-16 16-18 UART Fractional Precision Divider Control Registers (UFPDn) ............................ 16-17 16-19 UART Input Port Registers (UIPn)........................................................................... 16-18 16-20 UART Output Port Command Registers (UOP1/UOP0).......................................... 16-18 16-21 UART Block Diagram Showing External and Internal Interface Signals ................ 16-19 16-22 UART/RS-232 Interface ........................................................................................... 16-20 16-23 Clocking Source Diagram......................................................................................... 16-21 16-24 Transmitter and Receiver Functional Diagram......................................................... 16-23 16-25 Transmitter Timing .................................................................................................. 16-24 16-26 Receiver Timing........................................................................................................ 16-25 16-27 Automatic Echo ........................................................................................................ 16-28 16-28 Local Loop-Back ...................................................................................................... 16-28 16-29 Remote Loop-Back ................................................................................................... 16-29 16-30 Multidrop Mode Timing Diagram ............................................................................ 16-30 16-31 UART Mode Programming Flowchart ..................................................................... 16-32 17-1 Port A Control Register (PACNT).............................................................................. 17-3 17-2 Port B Control Register (PBCNT) .............................................................................. 17-5 17-3 Port D Control Register (PDCNT).............................................................................. 17-8 17-4 Port A Data Direction Register (PADDR)................................................................ 17-10 17-5 Port B Data Direction Register (PBDDR) ................................................................ 17-10 17-6 Port C Data Direction Register (PCDDR) ................................................................ 17-11 17-7 Port x Data Register (PADAT, PBDAT, and PCDAT) ............................................ 17-11 18-1 PWM Block Diagram (3 Identical Modules).............................................................. 18-1
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Figure Number 18-2 18-3 18-4 19-1 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 20-22 20-23 20-24 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 22-1 22-2 23-1 23-2 23-3 Title Page Number
PWM Control Registers (PWCRn)............................................................................. 18-3 PWM Width Register (PWWDn) ............................................................................... 18-4 PWM Waveform Examples (PWCRn[EN] = 1)......................................................... 18-5 MCF5272 Block Diagram with Signal Interfaces ...................................................... 19-2 Internal Operand Representation ................................................................................ 20-5 MCF5272 Interface to Various Port Sizes .................................................................. 20-6 Longword Read; EBI = 00; 32-Bit Port; Internal Termination .................................. 20-9 Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination................................. 20-10 Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination 20-10 Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination 20-11 Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination . 20-11 Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination 20-12 Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State .. 20-12 Longword Read; EBI=11; 32-Bit Port; Internal Termination .................................. 20-13 Word Write; EBI=11; 16/32-Bit Port; Internal Termination .................................... 20-14 Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination.................... 20-15 Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination . 20-15 Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination ..................... 20-16 Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination .. 20-16 Longword Read with Address Setup and Address Hold; EBI = 11; 32-Bit Port, Internal Termination ................................................................................................. 20-17 Longword Write with Address Setup and Address Hold; EBI = 11; 32-Bit Port, Internal Termination ................................................................................................. 20-17 Example of a Misaligned Longword Transfer .......................................................... 20-19 Example of a Misaligned Word Transfer.................................................................. 20-19 Longword Write Access To 32-Bit Port Terminated with TEA Timing .................. 20-21 Master Reset Timing................................................................................................. 20-23 Normal Reset Timing................................................................................................ 20-24 Software Watchdog Timer Reset Timing ................................................................. 20-25 Soft Reset Timing ..................................................................................................... 20-27 Test Access Port Block Diagram ................................................................................ 21-2 TAP Controller State Machine.................................................................................... 21-4 Output Cell (O.Cell) (BC-1)....................................................................................... 21-5 Input Cell (I.Cell). Observe only (BC-4) ................................................................... 21-5 Output Control Cell (En.Cell) (BC-4)........................................................................ 21-6 Bidirectional Cell (IO.Cell) (BC-6) ........................................................................... 21-6 General Arrangement for Bidirectional Pins .............................................................. 21-7 Bypass Register........................................................................................................... 21-8 MCF5272 Pinout (196 MAPBGA)............................................................................. 22-1 196 MAPBGA Package Dimensions (Case No. 1128A-01) ...................................... 22-2 Clock Input Timing Diagram...................................................................................... 23-5 General Input Timing Requirements .......................................................................... 23-7 Read/Write SRAM Bus Timing.................................................................................. 23-9
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Figure Page Title Number Number 23-4 SRAM Bus Cycle Terminated by TA....................................................................... 23-10 23-5 SRAM Bus Cycle Terminated by TEA .................................................................... 23-11 23-6 Reset and Mode Select/HIZ Configuration Timing.................................................. 23-11 23-7 Real-Time Trace AC Timing .................................................................................... 23-12 23-8 BDM Serial Port AC Timing .................................................................................... 23-12 23-9 SDRAM Signal Timing ............................................................................................ 23-14 23-10 SDRAM Self-Refresh Cycle Timing ........................................................................ 23-15 23-11 MII Receive Signal Timing Diagram ....................................................................... 23-16 23-12 MII Transmit Signal Timing Diagram...................................................................... 23-17 23-13 MII Async Inputs Timing Diagram .......................................................................... 23-17 23-14 MII Serial Management Channel Timing Diagram .................................................. 23-18 23-15 Timer Timing ............................................................................................................ 23-19 23-16 UART Timing........................................................................................................... 23-20 23-17 IDL Master Timing ................................................................................................... 23-21 23-18 IDL Slave Timing ..................................................................................................... 23-22 23-19 GCI Slave Mode Timing........................................................................................... 23-23 23-20 GCI Master Mode Timing ........................................................................................ 23-24 23-21 General-Purpose I/O Port Timing............................................................................. 23-25 23-22 USB Interface Timing............................................................................................... 23-26 23-23 IEEE 1149.1 (JTAG) Timing.................................................................................... 23-27 23-24 QSPI Timing ............................................................................................................. 23-28 23-25 PWM Timing ............................................................................................................ 23-29 B-1 Buffering and Termination ...........................................................................................B-2
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Table Number Title Page Number
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 5-5
CCR Field Descriptions ............................................................................................... 2-7 MOVEC Register Map ................................................................................................. 2-8 Status Field Descriptions .............................................................................................. 2-9 Integer Data Formats................................................................................................... 2-10 ColdFire Effective Addressing Modes....................................................................... 2-13 Notational Conventions ............................................................................................. 2-14 User-Mode Instruction Set Summary ......................................................................... 2-16 Supervisor-Mode Instruction Set Summary............................................................... 2-19 Misaligned Operand References ................................................................................ 2-20 Move Byte and Word Execution Times...................................................................... 2-21 Move Long Execution Times..................................................................................... 2-21 Move Execution Times .............................................................................................. 2-22 One-Operand Instruction Execution Times ................................................................ 2-22 Two-Operand Instruction Execution Times................................................................ 2-23 Miscellaneous Instruction Execution Times............................................................... 2-24 General Branch Instruction Execution Times............................................................. 2-25 Bcc Instruction Execution Times............................................................................... 2-26 Exception Vector Assignments................................................................................... 2-27 Format Field Encoding ............................................................................................... 2-28 Fault Status Encodings................................................................................................ 2-28 MCF5272 Exceptions ................................................................................................. 2-29 MAC Instruction Summary........................................................................................... 3-4 Memory Map of Instruction Cache Registers............................................................... 4-2 RAMBAR Field Description ........................................................................................ 4-3 Examples of Typical RAMBAR Settings ..................................................................... 4-5 ROMBAR Field Description ........................................................................................ 4-6 Examples of Typical ROMBAR Settings ..................................................................... 4-7 Instruction Cache Operation as Defined by CACR[CENB,CEIB]............................. 4-12 Memory Map of Instruction Cache Registers............................................................. 4-13 CACR Field Descriptions ........................................................................................... 4-13 ACRn Field Descriptions............................................................................................ 4-15 Debug Module Signals.................................................................................................. 5-2 Processor Status Encoding............................................................................................ 5-3 BDM/Breakpoint Registers........................................................................................... 5-6 Rev. A Shared BDM/Breakpoint Hardware ................................................................. 5-7 AATR Field Descriptions ............................................................................................. 5-8
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Table Number 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 8-5 9-1 Title Page Number
ABLR Field Description ............................................................................................... 5-9 ABHR Field Description............................................................................................... 5-9 CSR Field Descriptions............................................................................................... 5-10 DBR Field Descriptions.............................................................................................. 5-12 DBMR Field Descriptions .......................................................................................... 5-12 Access Size and Operand Data Location .................................................................... 5-12 PBR Field Descriptions............................................................................................... 5-13 PBMR Field Descriptions ........................................................................................... 5-13 TDR Field Descriptions .............................................................................................. 5-14 Receive BDM Packet Field Description ..................................................................... 5-18 Transmit BDM Packet Field Description ................................................................... 5-18 BDM Command Summary ......................................................................................... 5-19 BDM Field Descriptions ............................................................................................. 5-20 Control Register Map.................................................................................................. 5-31 Definition of DRc Encoding--Read........................................................................... 5-33 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................... 5-34 PST/DDATA Specification for User-Mode Instructions............................................ 5-37 PST/DDATA Specification for Supervisor-Mode Instructions.................................. 5-41 SIM Registers................................................................................................................ 6-3 MBAR Field Descriptions ........................................................................................... 6-5 SCR Field Descriptions................................................................................................. 6-5 SPR Field Descriptions ................................................................................................. 6-7 PMR Field Descriptions................................................................................................ 6-8 USB and USART Power Down Modes ...................................................................... 6-10 Exiting Sleep and Stop Modes.................................................................................... 6-11 DIR Field Descriptions ............................................................................................... 6-12 WRRR Field Descriptions .......................................................................................... 6-13 WIRR Field Descriptions............................................................................................ 6-13 WER Field Descriptions ............................................................................................. 6-14 Interrupt Controller Registers ....................................................................................... 7-2 Interrupt and Power Management Register Mnemonics .............................................. 7-3 ICR Field Descriptions ................................................................................................. 7-5 ISR Field Descriptions.................................................................................................. 7-7 PITR Field Descriptions ............................................................................................... 7-7 PIWR Field Descriptions .............................................................................................. 7-8 PIVR Field Descriptions ............................................................................................... 7-9 MCF5272 Interrupt Vector Table ................................................................................. 7-9 CSCR and CSOR Values after Reset............................................................................ 8-2 CSBRn Field Descriptions............................................................................................ 8-3 Output Read/Write Strobe Levels versus Chip Select EBI Code ................................. 8-4 Chip Select Memory Address Decoding Priority ......................................................... 8-5 CSORn Field Descriptions............................................................................................ 8-5 SDRAM Controller Signal Descriptions ...................................................................... 9-2
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Table Number 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 Title Page Number
Connecting BS[3:0] to DQMx ...................................................................................... 9-4 Configurations for 16-Bit Data Bus.............................................................................. 9-4 Configurations for 32-Bit Data Bus.............................................................................. 9-4 Internal Address Multiplexing (16-Bit Data Bus) ........................................................ 9-5 Internal Address Multiplexing (32-Bit Data Bus) ........................................................ 9-5 SDCR Field Descriptions.............................................................................................. 9-7 SDTR Field Descriptions.............................................................................................. 9-8 SDRAM Controller Performance, 32-Bit Port, (RCD = 0, RP = 1) or (RCD = 1, RP = 0) ...................................................................................................... 9-10 SDRAM Controller Performance, 32-Bit Port, (RCD = 0, RP = 0)........................... 9-11 SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port ............................ 9-11 SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=1) or (RCD=1, RP = 0) ........................................................................................................ 9-12 SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=0) ............................... 9-12 DMA Data Transfer Matrix ........................................................................................ 10-1 DMR Field Descriptions ............................................................................................. 10-3 DIR Field Descriptions ............................................................................................... 10-4 MII Mode .................................................................................................................... 11-3 Seven-Wire Mode Configuration................................................................................ 11-4 Ethernet Address Recognition .................................................................................... 11-7 Transmission Errors .................................................................................................. 11-10 Reception Errors ....................................................................................................... 11-10 FEC Register Memory Map...................................................................................... 11-11 ECR Field Descriptions ............................................................................................ 11-12 EIR Field Descriptions.............................................................................................. 11-13 EIMR Register Field Descriptions............................................................................ 11-14 IVSR Field Descriptions ........................................................................................... 11-15 RDAR Register Field Descriptions........................................................................... 11-16 TDAR Field Descriptions ......................................................................................... 11-16 MMFR Field Descriptions ........................................................................................ 11-17 MSCR Field Descriptions ......................................................................................... 11-19 Programming Examples for MSCR Register............................................................ 11-19 FRBR Field Descriptions.......................................................................................... 11-20 FRSR Field Descriptions .......................................................................................... 11-21 TFWR Field Descriptions ......................................................................................... 11-21 TFSR Field Descriptions........................................................................................... 11-22 RCR Field Descriptions ............................................................................................ 11-23 MFLR Field Descriptions ......................................................................................... 11-24 TCR Field Descriptions ............................................................................................ 11-25 MALR Field Descriptions......................................................................................... 11-26 MAUR Field Descriptions ........................................................................................ 11-26 HTUR Field Descriptions ......................................................................................... 11-27 HTLR Field Descriptions.......................................................................................... 11-28
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Table Number 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 Title Page Number
ERDSR Field Descriptions ....................................................................................... 11-28 ETDSR Field Descriptions ....................................................................................... 11-29 EMRBR Field Descriptions ...................................................................................... 11-30 Hardware Initialization ............................................................................................. 11-30 ETHER_EN = 0 ........................................................................................................ 11-30 User Initialization Process (before ETHER_EN) ..................................................... 11-31 User Initialization (after ETHER_EN) ..................................................................... 11-31 RxBD Field Descriptions.......................................................................................... 11-33 TxBD Field Descriptions .......................................................................................... 11-35 USB Device Requests ................................................................................................. 12-6 USB Memory Map...................................................................................................... 12-7 FNR Field Descriptions .............................................................................................. 12-9 FNMR Field Descriptions......................................................................................... 12-10 RFMR Field Descriptions ......................................................................................... 12-10 RFMMR Field Descriptions ..................................................................................... 12-11 FAR Field Descriptions ............................................................................................ 12-11 ASR Field Descriptions ............................................................................................ 12-12 SPECR Field Descriptions........................................................................................ 12-13 EP0SR Field Descriptions......................................................................................... 12-14 IEP0CFG Field Descriptions .................................................................................... 12-15 EP0CTL Field Descriptions...................................................................................... 12-17 EPnCTL Field Descriptions...................................................................................... 12-19 EP0IMR and EP0ISR Field Descriptions ................................................................. 12-21 EPnISR Field Descriptions ....................................................................................... 12-23 EPnIMR Field Descriptions...................................................................................... 12-24 EPnDR Field Descriptions........................................................................................ 12-25 EPnDPR Field Descriptions...................................................................................... 12-26 USB FIFO Access Timing ........................................................................................ 12-28 Example FIFO Setup................................................................................................. 12-30 PLIC Module Memory Map ..................................................................................... 13-14 P0CR-P3CR Field Descriptions ............................................................................... 13-19 PLCR Field Description............................................................................................ 13-21 P0ICR-P3ICR Field Descriptions ............................................................................ 13-21 P0PSR-P3PSR Field Descriptions ........................................................................... 13-23 PASR Field Descriptions .......................................................................................... 13-24 P0GMR-P3GMR Field Descriptions ....................................................................... 13-25 P0GMT-P3GMT Field Descriptions........................................................................ 13-26 PGMTA Field Descriptions ...................................................................................... 13-27 PGMTS Field Descriptions....................................................................................... 13-27 P0GCIR-P3GCIR Field Descriptions....................................................................... 13-28 P0GCIT-P3GCIT Field Descriptions ....................................................................... 13-29 PGCITSR Field Descriptions.................................................................................... 13-30 PDCSR Field Descriptions ....................................................................................... 13-30
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Table Number 13-15 13-16 13-17 14-1 14-2 14-3 14-4 14-5 14-6 14-7 15-1 15-2 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 18-1 18-2 18-3 19-1 19-2 Title Page Number
PDRQR Field Descriptions....................................................................................... 13-31 P0SDR-P3SDR Field Descriptions .......................................................................... 13-32 PCSR Field Descriptions .......................................................................................... 13-33 QSPI Input and Output Signals and Functions ........................................................... 14-3 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate ............................ 14-7 QMR Field Descriptions ........................................................................................... 14-10 QDLYR Field Descriptions ...................................................................................... 14-11 QWR Field Descriptions........................................................................................... 14-12 QIR Field Descriptions ............................................................................................. 14-13 QCR0-QCR15 Field Descriptions............................................................................ 14-15 TMRn Field Descriptions ........................................................................................... 15-4 TERn Field Descriptions............................................................................................. 15-6 UART Module Programming Model.......................................................................... 16-3 UMR1n Field Descriptions ......................................................................................... 16-5 UMR2n Field Descriptions ......................................................................................... 16-7 USRn Field Descriptions ............................................................................................ 16-8 UCSRn Field Descriptions.......................................................................................... 16-9 UCRn Field Descriptions.......................................................................................... 16-10 UIPCRn Field Descriptions ...................................................................................... 16-12 UACRn Field Descriptions ....................................................................................... 16-13 UISRn/UIMRn Field Descriptions ........................................................................... 16-14 UTFn Field Descriptions........................................................................................... 16-16 URFn Field Descriptions .......................................................................................... 16-17 UFPDn Field Descriptions........................................................................................ 16-17 UIPn Field Descriptions............................................................................................ 16-18 UOP1/UOP0 Field Descriptions ............................................................................... 16-18 UART Module Signals ............................................................................................. 16-19 Transmitter FIFO Status Bits .................................................................................... 16-26 Receiver FIFO Status Bits ........................................................................................ 16-27 GPIO Signal Multiplexing .......................................................................................... 17-1 GPIO Port Register Memory Map .............................................................................. 17-2 PACNT Field Descriptions ......................................................................................... 17-3 Port A Control Register Function Bits........................................................................ 17-4 PBCNT Field Descriptions ......................................................................................... 17-6 Port B Control Register Function Bits ........................................................................ 17-7 PDCNT Field Descriptions ......................................................................................... 17-8 Port D Control Register Function Bits........................................................................ 17-9 PADDR Field Descriptions....................................................................................... 17-10 PWM Module Memory Map ...................................................................................... 18-2 PWCRn Field Descriptions......................................................................................... 18-3 PWWDn Field Descriptions ....................................................................................... 18-4 Signal Descriptions Sorted by Function ..................................................................... 19-3 Signal Name and Description by Pin Number.......................................................... 19-10
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Table Number 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 20-1 20-2 20-3 20-4 20-5 20-6 20-7 21-1 21-2 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 23-11 23-12 23-13 23-14 23-15 23-16 23-17 23-18 23-19 23-20 23-21 23-22 23-23 23-24 23-25 A-1 Title Page Number
Byte Strobe Operation for 32-Bit Data Bus.............................................................. 19-20 Byte Strobe Operation for 16-Bit Data Bus--SRAM Cycles.................................. 19-20 Byte Strobe Operation for 16-Bit Data Bus--SDRAM Cycles............................... 19-20 Connecting BS[3:0] to DQMx .................................................................................. 19-21 Processor Status Encoding........................................................................................ 19-38 MCF5272 Bus Width Selection ................................................................................ 19-39 MCF5272 CS0 Memory Bus Width Selection ......................................................... 19-39 MCF5272 High Impedance Mode Selection ............................................................ 19-39 ColdFire Bus Signal Summary .................................................................................. 20-1 Chip Select Memory Address Decoding Priority ....................................................... 20-4 Byte Strobe Operation for 32-Bit Data Bus................................................................ 20-6 Byte Strobe Operation for 16-Bit Data Bus--SRAM Cycles.................................... 20-7 Byte Strobe Operation for 16-Bit Data Bus--SDRAM Cycles................................. 20-7 Data Bus Requirement for Read/Write Cycles ........................................................... 20-8 External Bus Interface Codes for CSBRs ................................................................... 20-8 JTAG Signals .............................................................................................................. 21-3 Instructions.................................................................................................................. 21-7 Maximum Supply, Input Voltage and Storage Temperature ...................................... 23-1 Operating Temperature ............................................................................................... 23-2 Thermal Resistance..................................................................................................... 23-2 DC Electrical Specifications ...................................................................................... 23-3 I/O Driver Capability .................................................................................................. 23-3 Clock Input and Output Timing Specifications .......................................................... 23-5 Processor Bus Input Timing Specifications................................................................ 23-6 Processor Bus Output Timing Specifications ............................................................. 23-8 Debug AC Timing Specification .............................................................................. 23-12 SDRAM Interface Timing Specifications................................................................. 23-13 MII Receive Signal Timing ...................................................................................... 23-15 MII Transmit Signal Timing..................................................................................... 23-16 MII Async Inputs Signal Timing .............................................................................. 23-17 MII Serial Management Channel Timing ................................................................. 23-17 Timer Module AC Timing Specifications ................................................................ 23-18 UART Modules AC Timing Specifications.............................................................. 23-19 IDL Master Mode Timing, PLIC Ports 1, 2, and 3 ................................................... 23-20 IDL Slave Mode Timing, PLIC Ports 0-3 ................................................................ 23-21 GCI Slave Mode Timing, PLIC Ports 0-3................................................................ 23-22 GCI Master Mode Timing, PLIC PORTs 1, 2, 3 ...................................................... 23-23 General-Purpose I/O Port AC Timing Specifications............................................... 23-25 USB Interface AC Timing Specifications................................................................. 23-25 IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................... 23-26 QSPI Modules AC Timing Specifications................................................................ 23-28 PWM Modules AC Timing Specifications ............................................................... 23-28 On-Chip Module Base Address Offsets from MBAR ................................................. A-1
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Table Number A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 Title Page Number
CPU Space Registers Memory Map ............................................................................ A-2 On-Chip Peripherals and Configuration Registers Memory Map ............................... A-2 Interrupt Control Register Memory Map..................................................................... A-2 Chip Select Register Memory Map.............................................................................. A-3 GPIO Port Register Memory Map ............................................................................... A-3 QSPI Module Memory Map ........................................................................................ A-4 PWM Module Memory Map ....................................................................................... A-4 DMA Module Memory Map........................................................................................ A-4 UART0 Module Memory Map .................................................................................... A-4 UART1 Module Memory Map .................................................................................... A-6 SDRAM Controller Memory Map............................................................................... A-7 Timer Module Memory Map ....................................................................................... A-7 PLIC Module Memory Map ........................................................................................ A-7 Ethernet Module Memory Map ................................................................................... A-9 USB Module Memory Map ....................................................................................... A-10
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About This Book
The primary objective of this user's manual is to define the functionality of the MCF5272 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers' responsibility to be sure he is using the most recent version of the documentation. To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldfire.
Audience
This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5272. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire(R) architecture.
Organization
Following is a summary and brief description of the major sections of this manual: * * Chapter 1, "Overview," includes general descriptions of the modules and features incorporated in the MCF5272, focussing in particular on new features. Chapter 2, "ColdFire Core," provides an overview of the microprocessor core of the MCF5272. The chapter describes the organization of the Version 2 (V2) ColdFire 5200 processor core and an overview of the program-visible registers (the programming model) as they are implemented on the MCF5272. It also includes a full description of exception handling and a table of instruction timings. Chapter 3, "Hardware Multiply/Accumulate (MAC) Unit," describes the MCF5272 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). Chapter 4, "Local Memory." This chapter describes the MCF5272 implementation of the ColdFire V2 local memory specification. It consists of three major sections, as follows.
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Organization
-- Section 4.3, "SRAM Overview," describes the MCF5272 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM. -- Section 4.4, "ROM Overview," describes the MCF5272 on-chip static ROM. The ROM module contains tabular data that the ColdFire core can access in a single cycle. -- Section 4.5, "Instruction Cache Overview," describes the MCF5272 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. * * Chapter 5, "Debug Support," describes the Revision A hardware debug support in the MCF5272. Chapter 6, "System Integration Module (SIM)," describes the SIM programming model, bus arbitration, power management, and system-protection functions for the MCF5272. Chapter 7, "Interrupt Controller," describes operation of the interrupt controller portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. Chapter 8, "Chip Select Module," describes the MCF5272 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. Chapter 9, "SDRAM Controller," describes configuration and operation of the synchronous DRAM controller component of the SIM, including a general description of signals involved in SDRAM operations. It provides interface information for memory configurations using most common SDRAM devices for both 16- and 32-bit-wide data buses. The chapter concludes with signal timing diagrams. Chapter 10, "DMA Controller," provides an overview of the MCF5272's one-channel DMA controller intended for memory-to-memory block data transfers. This chapter describes in detail its signals, registers, and operating modes. Chapter 11, "Ethernet Module," describes the MCF5272 fast Ethernet media access controller (MAC). This chapter begins with a feature-set overview, a functional block diagram, and transceiver connection information for both MII and seven-wire serial interfaces. The chapter concludes with detailed descriptions of operation and the programming model. Chapter 12, "Universal Serial Bus (USB)," provides an overview of the USB module of the MCF5272, including detailed operation information and the USB programming model. Connection examples and circuit board layout considerations are also provided.
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Organization
The USB Specification, Revision 1.1 is a recommended supplement to this chapter. It can be downloaded from http://www.usb.org. Chapter 2 of this specification, Terms and Abbreviations, provides definitions of many of the words found here. * Chapter 13, "Physical Layer Interface Controller (PLIC)," provides detailed information about the MCF5272's physical layer interface controller, a module intended to support ISDN applications. The chapter begins with a description of operation and a series of related block diagrams starting with a high-level overview. Each successive diagram depicts progressively more internal detail. The chapter then describes timing generation and the programming model and concludes with three application examples. Chapter 14, "Queued Serial Peripheral Interface (QSPI) Module," provides a feature-set overview and description of operation, including details of the QSPI's internal RAM organization. The chapter concludes with the programming model and a timing diagram. Chapter 15, "Timer Module," describes configuration and operation of the four general-purpose timer modules, timer 0, 1, 2 and 3. Chapter 16, "UART Modules," describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5272, including example register values for typical configurations. Chapter 17, "General Purpose I/O Module," describes the operation and programming model of the three general purpose I/O (GPIO) ports on the MCF5272. The chapter details pin assignment, direction-control, and data registers. Chapter 18, "Pulse Width Modulation (PWM) Module," describes the configuration and operation of the pulse width modulation (PWM) module. It includes a block diagram, programming model, and timing diagram. Chapter 19, "Signal Descriptions," provides a listing and brief description of all the MCF5272 signals. Specifically, it shows which are inputs or outputs, how they are multiplexed, and the state of each signal at reset. The first listing is organized by function, with signals appearing alphabetically within each functional group. This is followed by a second listing sorted by pin number. Chapter 20, "w Bus Operation," describes the functioning of the bus for data-transfer operations, error conditions, bus arbitration, and reset operations. It includes detailed timing diagrams showing signal interaction. Operation of the bus is defined for transfers initiated by the MCF5272 as a bus master. The MCF5272 does not support external bus masters. Note that Chapter 9, "SDRAM Controller," describes DRAM cycles.
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Suggested Reading
*
Chapter 21, "IEEE 1149.1 Test Access Port (JTAG)," describes configuration and operation of the MCF5272 Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE 1149.1 standard and provides additional information specific to the MCF5272. For internal details and sample applications, see the IEEE 1149.1 document. Chapter 22, "Mechanical Data," provides a functional pin listing and package diagram for the MCF5272. Chapter 23, "Electrical Characteristics," describes AC and DC electrical specifications and thermal characteristics for the MCF5272. Because additional speeds may have become available since the publication of this book, consult Motorola's ColdFire web page, http://www.motorola.com/coldfire, to confirm that this is the latest information. Appendix A, "List of Memory Maps," provides the entire address-map for MCF5272 memory-mapped registers. Appendix B, "Buffering and Impedance Matching," provides some suggestions regarding interface circuitry between the MCF5272 and SDRAMs.
* *
This manual includes the following two appendixes: * *
This manual also includes an index.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture.
General Information
The following documentation provides useful information about the ColdFire architecture and computer architecture in general:
ColdFire Documentation
The ColdFire documentation is available from the sources listed on the back cover of this manual. Document order numbers are included in parentheses for ease in ordering. * * ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) User's manuals--These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The ColdFire Programmers Reference Manual. These include the following: -- -- -- --
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ColdFire MCF5102 User's Manual (MCF5102UM/AD) ColdFire MCF5202 User's Manual (MCF5202UM/AD) ColdFire MCF5204 User's Manual (MCF5204UM/AD) ColdFire MCF5206 User's Manual (MCF5206EUM/AD)
MCF5272 User's Manual MOTOROLA
Conventions
-- ColdFire MCF5206E User's Manual (MCF5206EUM/AD) -- ColdFire MCF5307 User's Manual (MCF5307UM/AD) * * -- ColdFire MCF5407 User's Manual (MCF5407UM/AD) ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield
Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.motorola.com/ColdFire/.
Conventions
This document uses the following notational conventions: MNEMONICS mnemonics italics 0x0 0b0 REG[FIELD] In text, instruction mnemonics are shown in uppercase. In code and tables, instruction mnemonics are shown in lowercase. Italics indicate variable command parameters. Book titles in text are set in italics. Prefix to denote hexadecimal number Prefix to denote binary number Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register. A 4-bit data unit An 8-bit data unit A 16-bit data unit1 A 32-bit data unit In some contexts, such as signal encodings, x indicates a don't care. Used to express an undefined numerical value NOT logical operator AND logical operator OR logical operator
nibble byte word longword x n & |
1The
only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length.
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Acronyms and Abbreviations
Acronyms and Abbreviations
Table i lists acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term ADC ALU AVEC BDM BIST BSDL CODEC DAC DMA DSP EA EDO FIFO GPIO I2C IEEE IFP IPL JEDEC JTAG LIFO LRU LSB lsb MAC MBAR MSB msb Mux NOP OEP PC PCLK Analog-to-digital conversion Arithmetic logic unit Autovector Background debug mode Built-in self test Boundary-scan description language Code/decode Digital-to-analog conversion Direct memory access Digital signal processing Effective address Extended data output (DRAM) First-in, first-out General-purpose I/O Inter-integrated circuit Institute for Electrical and Electronics Engineers Instruction fetch pipeline Interrupt priority level Joint Electron Device Engineering Council Joint Test Action Group Last-in, first-out Least recently used Least-significant byte Least-significant bit Multiply accumulate unit, also Media access controller Memory base address register Most-significant byte Most-significant bit Multiplex No operation Operand execution pipeline Program counter Processor clock Meaning
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Table i. Acronyms and Abbreviated Terms (Continued)
Term PLIC PLL PLRU POR PQFP PWM QSPI RISC Rx SIM SOF TAP TTL Tx UART USB Physical layer interface controller Phase-locked loop Pseudo least recently used Power-on reset Plastic quad flat pack Pulse width modulation Queued serial peripheral interface Reduced instruction set computing Receive System integration module Start of frame Test access port Transistor transistor logic Transmit Universal asynchronous/synchronous receiver transmitter Universal serial bus Meaning
Terminology Conventions
Table ii shows terminology conventions used throughout this document.
Table ii. Notational Conventions
Instruction Operand Syntax Opcode Wildcard cc Logical condition (example: NE for not equal) Register Specifications An Ay,Ax Dn Dy,Dx Rc Rm Rn Rw Ry,Rx Xi Any address register n (example: A3 is address register 3) Source and destination address registers, respectively Any data register n (example: D5 is data register 5) Source and destination data registers, respectively Any control register (example VBR is the vector base register) MAC registers (ACC, MAC, MASK) Any address or data register Destination register w (used for MAC instructions only) Any source and destination registers, respectively index register i (can be an address or data register: Ai, Di)
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Terminology Conventions
Table ii. Notational Conventions (Continued)
Instruction Operand Syntax Register Names ACC CCR MACSR MASK PC SR MAC accumulator register Condition code register (lower byte of SR) MAC status register MAC mask register Program counter Status register Port Name DDATA PST Debug data port Processor status port Miscellaneous Operands # y,x |
